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1edi eicedriver? enhanced 1EDI30J12CP single jfet driver ic industrial power control preliminary datasheet rev. 1.3, november 2014
edition 2014-11-12 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of cond itions or characteristics. with respect to any examples or hints given herein, any typical values stated he rein and/or any information regarding the application of the device, infineon technologies hereby discla ims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems and/ or automotive, aviation and aerospace applications or systems only wit h the express written approv al of infineon technologies , if a failure of such components can reasonably be expected to cause the failure of that life-support, automotive, aviation and aerospace device or system or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the heal th of the user or other persons may be endangered.
product type package 1EDI30J12CP pg-dso-19-4 1edi eicedriver? enhanced 1EDI30J12CP preliminary datasheet 2 rev. 1.3, 2014-11-12 single jfet driver ic product highlights ? single driver for normally-on jfet ? galvanic isolation ? signal transmission vi a coreless transformer ? supporting direct drive jfet topology features ? single channel isolated jfet driver ? optimized for 1200v infineon coolsic tm jfets ? extremely low propagation delay of typ. 80ns ? extremly high common mode transient immunity of 100v/ns ? minimal 3a rail-to-rail output ? safe turn off during start up ? supports bootstrap operation description ? the 1EDI30J12CP is an advanced single channel jfet ga te driver. the driver is built to drive a normally-on coolsic tm jfet together with a low voltage p-channel mosfet in a switching loss optimized direct drive jfet topology. ? the device consists of two galvanic separated parts. the input signals are ttl level compatible with a high- voltage capability of up to 17.5v. the output chip is directly driving a coolsic tm jfet and mosfet with rail to rail output stages. jfdrv vcc2 mdrv vcc1 gnd1 +5v to gnd in from controller 1edi30j12cx vee2 vreg cljfg en -25v to vcc2 gnd bsen lv mosfet coolsic tm jfet r gj r gm c vee2 c vreg c vcc1
eicedriver? enhanced 1EDI30J12CP preliminary datasheet 3 rev. 1.3, 2014-11-12 table of contents 1 pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 representative block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2.1 supply options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.2 normal start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.3 reverse start up with self-pinch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2.4 bootstrap supply mode and start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.1 active shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.2 interlock between mosfet gate and jfet gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3.3 bootstrap start up mode indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 driver supply set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 gate clamping diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3 reference layout, thermal layout, layout guide lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
eicedriver? enhanced 1EDI30J12CP pin configuration and description preliminary datasheet 4 rev. 1.3, 2014-11-12 1 pin configuration and description the pin configuration for 1EDI30J12CP in a pg -dso-19-4 wide body package is shown in figure 1 and table 1 . figure 1 pin configuration pg-dso-19-4 table 1 pin configuration 1EDI30J12CP in pg-dso-19-4, wide body pin symbol description 1 n.c. internally not connected 1) 2 bsen bootstrap enable for bootstrap operation connect this pin to vcc2, for non bootstrap operation to vreg 3cljfgreserved 2) 4 vreg voltage regulator output vreg is the output of the integrated linear r egulator and the negative power supply for the gate drivers 5 n.c. internally not connected 1) 6 vee2 negative power supply output side vee2 is the input of the integrated linear regulator 7 mdrv mosfet driver output 8 jfdrv jfet driver output 9 vcc2 positive power supply output side vcc2 is the positive supply input of the jfet driver and mosfet driver, connected to the sources of the jfet and the mosfet 10 n.c. internally not connected 1) 11 n.c. internally not connected 1) 12 n.c. internally not connected 1) 13 n.c. internally not connected 1) 14 n.c. internally not connected 1) pg-dso -19-4 (300mil) bsen cljfg mdrv vcc2 vreg vee2 jfdrv n.c. en in vcc1 gnd1 n.c. 8 7 6 5 2 3 4 1 9 10 13 14 17 19 15 18 n.c. n.c. n.c. n.c. 11 12 20 n.c. n.c.
eicedriver? enhanced 1EDI30J12CP pin configuration and description preliminary datasheet 5 rev. 1.3, 2014-11-12 15 en driver enable 17 gnd1 signal ground input side 18 in driver input 19 vcc1 positive supply input side 20 n.c. internally not connected 1) 1) pads of n.c. pins must be left unconnected, separat ed from each other and floating for maximum creepage/clearance distance 2) connect to jfdrv pin or leav e pin unconnected and floating table 1 pin configuration 1EDI30J12CP in pg-dso-19-4, wide body (cont?d) pin symbol description
eicedriver? enhanced 1EDI30J12CP representative block diagram preliminary datasheet 6 rev. 1.3, 2014-11-12 2 representative block diagram a simplified functional block diagram is given in figure 2 representing the principle functionality of the driver. figure 2 representative block diagram input logic logic voltage supply 1edi30j12cx uvlo x jfdrv x mdrv vreg uvlo x bsen linear regulator x vcc2 x vee2 x vreg x cljfg x vcc1 x in x gnd1 tx rx en x vcc2 vcc2 vreg
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 7 rev. 1.3, 2014-11-12 3 functional description 3.1 introduction the 1edi30j12cx is an advanced jfet (junction gate field-effe ct transistor) gate driver. the driver is built to drive a normally-on coolsic tm jfet together with a low voltage p-cha nnel mosfet in a switching loss optimized cascode operation called direct drive jfet topology. as mosfet (metal?oxide?semiconductor field-effect tr ansistor; referred to as pmos, lv mosfet) a 30 v p- channel optimos tm mosfet with low r dson is typically used (e.g. optimos tm bsc030p03ns3 g). the driver consists of two galvanic separated parts. the inputs can be co nnected to any cont roller with varying signal levels. the pins can handle signals up to 17 .5v, however the thresholds remains at ttl levels. the output side is connected to the high voltage side of th e application, incorporates tw o rail to rail output stages. the two gate drivers, one for the jfet and one for the mosfet, drive the gates between vcc2 and the regulated output vreg. the 1edi30j12cx supports two different start up mode s selectable by the bootstrap enable pin bsen. a specialized bootstrap operation mode for supplying the dr iver via a bootstrap diode. and a standard operation mode for direct supply realised with a floating isolated supply source. the output side has a built in linear voltage regulator to generate an accurate jfet driver supply voltage inside the window between pinch off voltage and pu nch through voltage of infineon?s coolsic tm jfets . in addition, the internal regulator separates the driver supply voltage from a common supply voltage for low side switches, so all low side switches could be supplied by one negative supply. further in isolat ed supply topologies it offers the support of wide supply range due to preregulation. so voltage drops due to bad transformer coupling can be handled. cascodes were introduced in the past for faster switching made possible by the elimination of the jfets cgd acting as a feedback to the control gate. the disadvantage by eliminating the feedback is that the dv/dt of the switch gets uncontrolled. new jfet devices like coolsic tm jfet offers a reduced gate charge, t herefore driving the jfet gate directly offers advantages in controlling the switch ing speed with lower emi and less ringing. 3.2 theory of operation the optimized cascode operation offered by the 1edi30j1 2cx driver called direct drive jfet topology differs from the normal cascode in the way it is controlling the switch. the normal cascode controls the normally-on jfet by indirectly controlling the source potential of the jfet via the low-voltage mosfet. in the direct drive jfet topology the mosfet is used to keep the normally-on jfet in a safe off-state during start up of the application as in the normal cascode. when the driver auxillia ry supply voltage is high enough to release the under voltage lock out (uvlo) the mosfet is permanently turned on and the jfet is driven directly according to the input signal. the input signal is transferred across the isolating coreless transformer (clt ) from input side to output side. a high at the input pin turns on the jfet. the 1edi30j12cx is a non inverting driver. when the vcc1 supply voltage has reached the turn on th reshold and the signal at the en pin is high, the input side is able to send the in signal to the output side. depending on the uvlo of the output side, the input signal is either ignored if |v vreg | is below the uvlo-on- threshold or is applied amplified at the gate of jfet. when the vcc1 voltage potential reaches the turn off thre shold, the input side sends an off signal to the output side to ensure a defined switch off state before the driver is disabled. the driver can be disabled using the en pin: in case the en pin is pulled to low, the output is switched off regardless of the signal applied to the in pin.
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 8 rev. 1.3, 2014-11-12 3.2.1 supply options two different isolated supply configurations are po ssible depending on the reference node of the supply. 1. the external power supply is related to vcc2 (see figure 3 high-side switch and figure 10 ). this configuration is possible for both high and low-side switches, but each driver has to be separately supplied in order to guarantee the correct start up behavior. it is not possible to share the same supply among more than one driver. 2. the external power supply is relat ed to the mosfet drain potential (see figure 3 low-side switches and figure 12 ). this allows for using the same powe r supply to more than one driver st age as long as their mosfet drains are connected to the same potential. which makes this configuration most suitable to be used on drivers connected to low-side switches. figure 3 application drawing fo r isolated supply (pfc+hb ) additionally it is possible to supply the driver via boots trapping. in this supply mode a high-side driverstage can share the same isolated high-side supply (see figure 6 ). it is also possible to transfer the power from the high- side to a low-side driverstage vi a a bootrapping capacitor (see figure 13 ). further information about the bootstapping supply can be found in chapter 3.2.4 . 3.2.2 normal start up this section describes a normal start up in which the auxiliary supplies of th e driver are enabled before a voltage is applied over the switch (jfet drain to pmos drain) . the timing diagram of this start up is shown in figure 4 . the negative driver supply voltage is applied to v ee2. vreg is following the supply voltage ramp with the regulator drop of ap proximately 2v, depending on the capacitor size and the ramping speed of vee2. when vreg reaches the uvlo threshold the driver is turning on the p-channel mosfet. after mdrv has reached the on- threshold the jfet gate driver stage is active and follows the in signals with a short propagation delay of typical 80ns. load jfdrv vcc2 mdrv vcc1 gnd1 +5v ls_in 1edi30j12cx c vcc1 vee2 vreg cljfg c vee2 c vreg in jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg -25v_hs gnd c c jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg -25v en vcc1 gnd1 +5v hs_in c vcc1 in gnd en vcc1 gnd1 +5v pfc_in c vcc1 in gnd en l1 n bsen bsen bsen hv supply
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 9 rev. 1.3, 2014-11-12 figure 4 principle start up, auxiliary supplies pre sent before a voltage is applied over the switch (signal names are chosen equivalent to the pin names of the driver) 3.2.3 reverse start up with self-pinch-off one of the biggest questions that arise when dealing with normally-on de vices is the situation that comes up when the auxiliary power supply fa ils or is not ready at the point when the high voltage is applied over the switch. this event is depicted in figure 5 . due to the normally-on behavior of the jfet and the cascoded normally-off mosfet, the voltage is being blocked at the mosfet. the vds voltage that is building up over the switched-off mosfet is being mirrored to the jfet vgs voltage via the diode connecting the mosfet drain to the jfet gate (see chapter 6.2 ) until the level reaches the jfet pinch off volt age and the jfet itself blocks the voltage. when the jfet is pinched off a sma ll current is still flowing through the jfet charging the c apacitors cvee2 and cvreg which supply the driver. in this way the jfet acts as a linear regulator powering the output stages of the driver at the pinch off voltage. as soon as the auxiliary supply is larg er than the pinch off vo ltage the auxiliary supply is charging vee2. as it reaches the under voltage lockout level, the jfet is ke pt off and the mosfet is turned on. from this point onwards the driver is transmitting the in signal to the jfet gate. this behavior of acting in a self-regulating manner enab les the driver to also work in a bootstrapping scheme. v vcc1on vcc1 in en v vcc1off output signals referenced to vcc2 vee2 bsen mdrv t pd on jfdrv t pd off_ en t pd off t pd on _ en vreg v vr ego n v vr ego ff
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 10 rev. 1.3, 2014-11-12 figure 5 principle start up with the auxiliary supplies not present when voltage is applied over the switch (signal names are chosen equivalent to the pin names of the driver) 3.2.4 bootstrap suppl y mode and start up in bootstrap supply mo de, the capacitors at vee2 and vreg are charge d to the pinch off voltage of the jfet as described in chapter 3.2.3 (infineon coolsic tm jfet family has the lowest gate threshold voltage at -12 v). when the bsen pin is connected to vcc2 the bootstrap supply mode is active. in this ca se a lower uvlo threshold is used and the driver is ac tive at approximately -9.0 v. after passing this lower uvlo threshold the driver is ready to receive in signals from the input stage. this input signal is transferred to a swit ching logic which turns on the p-channel mosfet. after the v mdrv has passed the mosfet gate turn on threshold the jfet is turned on. the voltage drop across the mosfet and jfet channel is nearly zero. the potential of vcc2 is identical to jfet drain voltage. a nega tive supply related to the jfet drain (positive potential of dc-link capacitor, half bridge supply) can charge the input capacitor c vee2 through a high voltage bootstrap diode. an example of a high-side boot strap supply can be seen in figure 6 . if the input stage is sending a low to the driving stage, first the jfet is tur ned off. after the jf drv has passed the off threshold the mosfet is turned off. the propagation delay in bootstrap mode is therefore en larged by the mosfet gate charging time. after vreg has passed the higher normal uvlo level, the mosfet is permanently kept on and the delay changes to the fast hv supply start up auxiliary s upply v vcc1on vcc1 in -25v aux en v vcc1off output signals referenced to vcc2 vee2 t pd on vreg mdrv jfdrv v vr ego n v vjfet _pinch_off v vr ego ff t pd o n _ en t pd off t pd off _ en
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 11 rev. 1.3, 2014-11-12 datasheet values of typical 80ns. a ti ming diagram showing the various signals in this startup mode is depicted in figure 7 . figure 8 shows a diagram detailin g the reason fo r the prolonged popagation delay. the longer propagation delay can be indicated to the in put side by using an optocoupler. the optocoupler diode is inserted between bsen and vcc2. du ring the start up phase in bootstrap mode bsen is applying an output current of at least 2 ma while in is high. during the bootstrap start up phase the power dissipation in the driver is increased. therefore, the controller has to make sure that the driver does not remain in bootstrap start up mode for longer periods of time in order not to overheat the driver. during the boostrap start-up phase, the propagation delay is larger and the effective jfet conduction time shorter compared to standard operating mode. this means, the controller has to take care to compensate for the longer propagation delays and shorter on-times, e.g. in a half-bri dge configuration, the dead-times have to be increased. after the start-up phase is finished, the controller has to reduce the dead-times to normal operating values, not to risk body-diode conduction over long periods of time, which can lead to higher power dissipation of the jfets. figure 6 application drawing for high side bootstrap supply (fb) jfdrv vcc2 mdrv vcc1 gnd1 +5v ls_in 1edi30j12cx c vcc1 vee2 vreg cljfg c vee2 c vreg in jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg -25v_h gnd c c jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg -25v en vcc1 gnd1 +5v ls_in c vcc1 in gnd en vcc1 gnd1 +5v ls_in c vcc1 in gnd en 800v jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg vcc1 gnd1 +5v ls_in c vcc1 in gnd en bsen bsen bsen bsen
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 12 rev. 1.3, 2014-11-12 figure 7 start up bootstrap supply mode for high side located cascodes (bsen connected to vcc2) (signal names are chosen equivalent to the pin names of the driver) figure 8 timing of in to jfdrv, a) normal mode, b) bootstrap mode hv supply v vcc1on vcc1 in start up auxiliary supply vee2 t pd on bs vreg mdrv jfdrv v vr ego n t pdoffbs v vjfet _pinch_off v vr ego n bs bootstrap start up phase t pd on i_bsen output signals referenced to vcc2 v vr egoff t pd on bs t pdoffbs v vcc1off t pd on _ en t pd off t pd off _ en en in mdrv jfdrv t pd on bs 50% t pdoffbs vcc2-1. 9v 50 % in mdrv jfdrv t pd on 50 % t pd off vcc2-19v 50 % a) b)
eicedriver? enhanced 1EDI30J12CP functional description preliminary datasheet 13 rev. 1.3, 2014-11-12 3.3 protection features 3.3.1 active shut down the active shut down feature ensures mosfet off-state under all circumstances even if the output side supply is inactive. the p-channel mosfet ga te is held actively high until v reg is passing the output uvlo thresholds of the driver. 3.3.2 interlock between mosf et gate and jfet gate the jfet can only be switched on, if the mosfet is on , otherwise the low voltage mosfet will be destroyed by overvoltage. to ensure proper operatio n of the cascode, the driver is monitoring the mosfet gate voltage at mdrv pin and the jfet gate voltage at jfdrv pin. only if the mosfet is on, indicated by mdrv pin having low potential, the jfet is allowe d to turn on. similar in opposite direction, mosfet turn off is on ly allowed if the jfet is in its off state. 3.3.3 bootstrap start up mode indicator the 1edi30j12cx indicates at bsen pin that the driver ha s entered the boot strap start up p hase with an output current of min 2ma to drive an opto coupler if in signal is driven high.
eicedriver? enhanced 1EDI30J12CP characteristics preliminary datasheet 14 rev. 1.3, 2014-11-12 4 characteristics unless otherwise noticed, voltages of the input side sig nals (pins vcc1, in, en, gnd1) are measured with respect to input ground (pin gnd1), all other voltages are meas ured with respect to positive output supply (pin vcc2). currents in the following tables are defined as positive cu rrents flowing out of the pi n (unless otherwise specified). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings absolute maximum ratings are listed in table 2 . stresses above the max. values may cause permanent damage to the device. exposure to absolute ma ximum rating conditions for extended periods may af fect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. for the same reason make su re that any capacitors that will be connected to pins vcc1 and vcc2 are discharged before assembling the application circuit. table 2 absolute maximum ratings parameter symbol limit values unit remarks min. max. positive supply voltage input side v vcc1 -0.3 18 v voltage at pin in, en v in -0.3 v vcc1 +0.3 v input to output isolating voltage v iso -1200 +1200 v 1) 1) with reference to gnd1 negative supply voltage output side (vee2) v vee2 -30 v vcc2 +0.3 v voltage at pin bsen v bsen v vreg -0.3 v vcc2 +0.3 v voltage at pin vreg v vreg -21 v vcc2 +0.3 v vee2 max dv/dt |dv vee2 | 125 v/ms c vreg = 2.2f voltage at pin jfdrv v jfdrv v vreg -0.3 v vcc2 +0.3 v voltage at pin mdrv v mdrv v vreg -0.3 v vcc2 +0.3 v junction temperature t j -40 150 c storage temperature t s -55 150 c 2)3) 2) prolonged storage at high temperatures reduces the lifetime of the product 3) tested according to eia/jesd22-a103d maximum power dissipation p tot 1.0 w pg-dso-19-4, t a =25c esd capability v esd ? 2 kv human body model 4) 4) according to eia/jesd22-a114-b (discharging at 100pf capacitor through 1.5k resistor)
eicedriver? enhanced 1EDI30J12CP characteristics preliminary datasheet 15 rev. 1.3, 2014-11-12 4.2 thermal characteristics 4.3 operating range table 3 thermal characteristics parameter symbol values unit remarks typ. thermal resistance junction-ambient r thja25 85 k/w pg-dso-19-4, t a =25c; layout: figure 16 table 4 operating range parameter symbol limit values unit remarks min. max. positive supply voltage input side v vcc1 4.75 17.5 v logic input voltage input side (in, en) v in 0v vcc1 v negative supply voltage output side (vee2) v vee2 -28 -22 v vreg in regulation, full psrr negative supply voltage output side (vee2) v vee2 -28 -19 v v vreg > v vregoff 1) output capacitance for vreg c vreg 0.22 2.2 f from vreg to vcc2 1) , esr cvreg < 15mohm common mode transient immunity |dv iso /dt| ? 100 v/ns 1) 1) the parameter is not subject to production test - verified by design/characterization junction temperature t j -40 150 c 1)2) 2) according to product qualification condit ions (tested according to eia/jesd22-a108d)
eicedriver? enhanced 1EDI30J12CP characteristics preliminary datasheet 16 rev. 1.3, 2014-11-12 4.4 electrical characteristics the electrical characteristics involve the spread of valu es given within the specifie d supply voltage and junction temperature range t j from -40c to 150c. typical values represent the nominal values related to t j =25c. unless otherwise noticed, voltages of the input side sig nals (pins vcc1, in, en, gnd1) are measured with respect to input ground (pin gnd1) all other voltages are measur ed with respect to positive output supply (pin vcc2). supply voltages are v vcc1 = 5 v and v vee2 = -25 v if not otherwise mentioned. the following characteristics are specified ? power supply ( table 5 ) ? logic input ( table 6 ) ? jfet driver ( table 7 ) ? mosfet driver ( table 8 ) ? dynamic characteristics ( table 9 ) table 5 power supply parameter symbol values unit note / test condition min. typ. max. vcc1 quiescent current i vcc1qu1 ? 430 650 a in = statically low, en = statically high vcc1 quiescent current i vcc1qu2 120 240 500 a en = statically low vcc1 supply current i vcc1supp ? 1.2 1.6 ma in = 1mhz vcc1 turn on threshold v vcc1on 4.15 4.55 4.75 v vcc1 turn off threshold v vcc1off 3.9 4.25 4.55 v vcc1 turn on/off hysteresis v vcc1hys 0.15 v vee2 quiescent current 1 i vee2qu1 ? 380 500 a output chip off due to uvlo vee2 quiescent current 2 i vee2qu2 ? 800 1100 a in = low, output chip on vreg output voltage 1)2) 1) voltage refer to vcc2 2) dc voltage v vreg0 -19.5 -18.85 -18.1 v 1f from vreg to vcc2, v vee2 < -22v, load 0ma vreg output voltage loaded 1)2) v vreg50 -19.0 -18.25 -17.5 v 1f from vreg to vcc2, v vee2 < -22v, load 50ma vreg turn on threshold 1)3) 3) ulvo threshold output chip v vregon -17.4 -16.9 -16.4 v vreg turn off threshold 1)3) v vregoff -17.0 -16.4 -16.0 v vreg turn on/off hysteresis 1)3) v vreghys 0.5 v vreg turn on threshold bs 1)3) v vregonbs -9.8 -9.5 -9.0 v v bsen > -3v 1) vreg turn off threshold bs 1)3) v vregoffbs -9.2 -8.8 -8.3 v v bsen > -3v 1) vreg turn on/off hysteresis bs 1)3) v vreghysbs 0.7 v v bsen > -3v 1) vreg load current i vreg 50 ma including loads from mdrv and jfdrv
eicedriver? enhanced 1EDI30J12CP characteristics preliminary datasheet 17 rev. 1.3, 2014-11-12 table 6 logic input parameter symbol values unit note / test condition min. typ. max. in, en low input voltage v inl 1.0 v in, en high input voltage v inh 2.0 v in, en input current in 30 400 a v in =v vcc1 bsen low input voltage v bsenl v vreg + 2.0 v bsen high input voltage v bsenh v vreg + 3.0 v bsen output current bsen -3.5 -2 ma v bsen > v vreg + 5.7v, v in = high, v vregon < v vreg < v vregonbs bsen output current bsenpd -70 -38 -15 a v in = low table 7 jfet driver (reference is vcc2) parameter symbol values unit note / test condition min. typ. max. high level output voltage v jfdrvh -2.0 -1.75 v i jfdrv =200ma; -4.0 -3.5 v i jfdrv =2a; ?-4.1 vi jfdrv =3a 1) high level output peak current i jfdrvh 3.0 4.0 a 1) output voltage at low state v jfdrvl v vreg + 0.17 v vreg + 0.35 vi jfdrv =-200ma; v vreg + 1.9 v vreg + 4.0 vi jfdrv =-2a; ?3.0 vi jfdrv =-3a 1) 1) the parameter is not subject to production test - verified by design/characterisation low level output peak current i jfdrvl -3.0 -4.0 a 1) rise time jfdrv t jfdrvr ?2330nsc loadj = 4.7 nf, vl=20% to vh 80% fall time jfdrv t jfdrvf ?2235ns table 8 mosfet driver (reference is vcc2) parameter symbol values unit note / test condition min. typ. max. high level output voltage v mdrvh -1.75 -1.35 v i mdrv =150ma -4.0 -3.15 v i mdrv =1.5a
eicedriver? enhanced 1EDI30J12CP characteristics preliminary datasheet 18 rev. 1.3, 2014-11-12 high level output peak current i mdrvh 23 a 1) output voltage at low state v mdrvl v vreg +0.26 v vreg +0.55 vi mdrv =-150ma v vreg +1.0 v vreg -2.1 vi mdrv =-0.5a 2.0 ? v i mdrv =-1.0a 1) low level output peak current i mdrvl -2 -1 a 1) rise time mdrv t mdrvr 65 110 ns v vreg =19v, c loadm = 22 nf, vl 20% to vh 80% fall time mdrv t mdrvf 165 270 ns 1) the parameter is not subject to production test - verified by design/characterisation table 9 dynamic characteristics parameter symbol values unit note / test condition min. typ. max. input to output propagation delay on (in: l to h) t pdon 53 80 106 ns v vcc1 =5v, c loadj = 100 pf, v in =50%, v jfdrv =50%, v en =h t j =25c input to output propagation delay off (in: h to l) t pdoff 53 80 106 ns enable to output propagation delay on (en: l to h) t pdon_en 170 290 390 ns v vcc1 =5v, c loadj = 100 pf, v en =50%, v jfdrv =50%, v in =h enable to output propagation delay off (in: h to l) t pdoff_en 60 110 140 ns input to output propagation delay distortion t pdon -t pdoff t pddisto -4.0 12 ns v vcc1 =5v, c loadj = 100 pf, v in =50%, v jfdrv =50%, v en =h input to output propagation delay distortion due to temp t pddistot -20 20 ns 1) 1) the parameter is not subject to production test - verified by design/characterisation input to output propagation delay on bootstrap mode 2) 2) see figure 8 t pdonbs 300 ns v vreg =-19v, v vcc1 =5v, c loadj = 100 pf, c loadm =22nf, v in =50%, v jfdrv =50% input to output propagation delay off bootstrap mode 2) t pdoffbs 300 ns v vreg =-19v, v vcc1 =5v, c loadj = 100 pf, c loadm =22nf, v in =50%, v mdrv =-1.9v in input pulse surpression t minin 29 40 68 ns switching frequency f sw 2mhzv vcc1 =5v table 8 mosfet driver (reference is vcc2) (cont?d) parameter symbol values unit note / test condition min. typ. max.
eicedriver? enhanced 1EDI30J12CP outline dimensions preliminary datasheet 19 rev. 1.3, 2014-11-12 5 outline dimensions figure 9 pg-dso-19-4 0.512 0.104 0.020 0.013 0.419 0.299 0.050 millimeters l t h f3 f2 f1 d dim a1 a b c e e1 n e - min 19 0.016 0 8 0.30 max inches 19 0.050 bsc 0.496 min - 0.004 0.012 0.009 0.394 0.291 max 0.012 scale 1.0 0 2mm 0 1.0 0.10 2.65 0.51 0.32 13.00 10.65 7.60 7.40 10.00 12.60 0.23 0.30 1.27 0.40 8 0 1.27 bsc 02 issue date 19.04.2011 document no. z8b00160774 european projection revision 9.73 0.65 1.67 0.383 0.026 0.066 footprint 0.030 0.010 0.75 0.25
eicedriver? enhanced 1EDI30J12CP outline dimensions preliminary datasheet 20 rev. 1.3, 2014-11-12 notes 1. you can find all of our packages, sorts of packing an d others in our infineon internet page ?products?: http://www.infineon.com/cms/en /product/technology/packages/ .
eicedriver? enhanced 1EDI30J12CP application hints preliminary datasheet 21 rev. 1.3, 2014-11-12 6 application hints this chapter gives some hints on how the auxiliary supplies can be set up to supply the driver. 6.1 driver supply set up figure 10 shows the standard topology wher e the auxiliary supply is connected between vcc2 and vee2. in this case the internal regulator is used to create the -19 v vreg supply. figure 10 isolated and floating supply, a) cascode configuration, b) only jfet it is also possible to supply the driver with -19 v directly. in this case (shown in figure 11 ) the pins vreg and vee2 are shorted and cvee2 as well as the corres ponding diode are not ne eded. it has to be ma de sure that the -19 v supply is accurate within +/- 5 %. figure 11 isolated and floating direct supply, a) cascode configuration, b) only jfet the third option of connecting the auxiliary supply is to connect it between the mosfet drain and vee2 ( figure 12 ). since the auxiliary power supply is not connected to the reference n ode of the driver stage (vcc2) an additional 10 ? resistor is needed between t he power supply an d the vee2 pin. this resi stor limits the current coming from the supply when current is switched thro ugh the mosfet. when a current is switched through the mosfet a voltage is induced in the parasitic inductanc es of the mosfet which leads to a voltage difference between the reference node of the driver and the supply reference node. as in the first described method the internal regulator is active and supplies the driver stages with the needed -19 v. when using this power supply option for switches which mosfet drains are connected to the same node and potential one power supply can be used to power two or more driver stages. the best example are the low side switches in a h-bridge (see figure 6 and figure 14 ). jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg vcc1 gnd1 +5v in c vcc1 in gnd en bsen isolated, floating -22v ? -28v jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg -22v ? -28v vcc1 gnd1 +5v in c vcc1 in gnd en bsen isolated, floating a) b) jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vreg vcc1 gnd1 +5v in c vcc1 in gnd en bsen isolated, floating -19 v + /- 5 % jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vreg -19v +/- 5% vcc1 gnd1 +5v in c vcc1 in gnd en bsen isolated, floating a) b)
eicedriver? enhanced 1EDI30J12CP application hints preliminary datasheet 22 rev. 1.3, 2014-11-12 figure 12 mosfet drain related supply an alternative method of supplying th e low-side driver is via a bootstra pping scheme from the high-side supply (shown in figure 13 ). this cascaded bootstrap s upply transfers the needed energy via a bootstrapping capacitor (c bs ) to the low-side. additional information on how to activate the bootstrap mode can be found in chapter 3.2.4 bootstrap supply mode and start up . figure 13 cascaded bootstrap supply, a) cascode configuration, b) only jfet in case a normally off behavior is not needed or desired the jfet can be used without the cascoded mosfet. topologies depicting a normally on circuit are shown in figure 10 b), figure 11 b) and figure 13 b). in these cases a short circuit in a failure event cannot be pr evented due to the fact that every safety aspect of the direct drive jfet topo logy is deactivated. +5v in c vcc1 gnd jfdrv vcc2 mdrv vcc1 gnd1 1edi30j12cx vee2 vreg cljfg c vee2 c vreg in en bsen -22 v ? - 28 v isolated, fixed jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg vcc1 gnd1 +5v hs_in c vcc1 in gnd en bsen hv supply hv related bootstrap hs -19 v ? -28v jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg vcc1 gnd1 +5v ls_in c vcc1 in gnd en bsen bootstrap ls jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 vcc1 gnd1 +5v hs_in c vcc1 in gnd en bsen hv supply hv related bootstrap hs -19v ? -28v jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg vcc1 gnd1 +5v ls_in c vcc1 in gnd en bsen c vreg a) b) c bs bootstrap ls
eicedriver? enhanced 1EDI30J12CP application hints preliminary datasheet 23 rev. 1.3, 2014-11-12 figure 14 application drawing for high side bootstra p supply (fb), low-side normally-on (refer to figure 6 for low-side no rmally-off variant) figure 14 shows a full bridge with a norma lly-on low-side configuration. the high-side stages are powered with bootstrapping while the low-side stages are powered with an isolated and fixed supply that is gnd related. the corresponding normally-off variant can be seen in figure 6 6.2 gate clamping diode the external gate clamping diode connects the jfet ga te to the mosfet drain pote ntial. in case the auxiliary power supply of the driver is not active due to power su pply failure or reverse startup this diode ensures the normally-off behavior of the circuit. due to the normally-on behavior of the jfet and the casc oded normally-off mosfet, the voltage is being blocked at the mosfet. the vds voltage that is building up over the switched-off mosfet is being mirrored to the jfet vgs voltage via gate clamping diode connecting the mosfet drain to the jfet gate until the level reaches the jfet pinch off voltage and the jfet itself blocks the voltage (see chapter 3.2.3 ). the voltage rating of the diode is mainly depenent on the parasitic inductance between jfet source and mosfet drain times the current change over time. an in fineon bas16 diode capable of blocking 80 v should be sufficient for most layouts. a resistor should be placed in series with the diode to limi t the current through the diode. it has to be matched to the maximum current rating of the used diode. typically it should be around 5 times larger than the gate resistance in order not to slow down the turn-on of the jfet. jfdrv vcc2 mdrv vcc1 gnd1 +5v ls_in 1edi30j12cx c vcc1 vee2 vreg cljfg c vee2 c vreg in jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg -25v_h gnd c c jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg c vee2 c vreg -25v en vcc1 gnd1 +5v ls_in c vcc1 in gnd en vcc1 gnd1 +5v ls_in c vcc1 in gnd en 800v jfdrv vcc2 mdrv 1edi30j12cx vee2 vreg cljfg c vee2 c vreg vcc1 gnd1 +5v ls_in c vcc1 in gnd en bsen bsen bsen bsen cljfg
eicedriver? enhanced 1EDI30J12CP application hints preliminary datasheet 24 rev. 1.3, 2014-11-12 6.3 reference layout, thermal layout, layout guide lines in this chapter the reference and thermal layouts are disp layed. please contact our local sales team for additional information about placement priorities. figure 15 typical layout of a1EDI30J12CP driver stage figure 16 thermal reference layout of a 1EDI30J12CP driver stage dcl rcl pmos bsc30p03ns3g 1EDI30J12CP in en cvcc1 rgm cvee2 cvreg dvreg dvee2 rgj cvcc1.2
eicedriver? enhanced 1EDI30J12CP application hints preliminary datasheet 25 rev. 1.3, 2014-11-12 figure 17 pcb stack - thermal reference layout 35 m copper 1.5mm 50x40x1.5mm fr4 35 m copper ther m al vias
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